The issue is how to manage a library of gschem transistor symbols and a library of PCB transistor elements such that we can be confident of correct pin number correspondence between the libraries. We need to understand how to handle the many permutations of emitter, base, and collector (e,b,c) pinouts and the variations of package number of pins and pin numbering. This doc shows the approach I've taken in my custom gschem symbols and PCB elements.
There are a couple of ways to consider:
It makes sense to me to say the second approach is obviously better. Setting up the gschem symbols is simple enough, just create the six symbols for each transistor type with the pin numbers of the emitter, base, and collector corresponding to the sequence indicated in the name. For example, the symbol npn-ebc.sym would have an emitter pinnumber attribute of 1, a base pinnumber attribute of 2 and a collector pinnumber attribute of 3. Now you only need to make PCB elements with correctly numbered pins for transistor packages as you need them and you need to have a systematic approach for naming these elements.
A point to keep in mind when looking at transistor package pin configurations and numbers is that a TO (Transistor Outline) designation is really only just that - a designation of a particular shaped and sized outline. It actually is not a specification of the pins coming out of that package. Manufacturers may have have a TO package designation qualified by their internal “case style” or “package number” code. This qualification determines the definition of the number of pins, the arrangement of the pins, and the pin numbering.
However, most TO packages do conform to a standard pin numbering convention and have a predominant number of pins and pin placement configuration. So it makes sense to have PCB elements with a particular TO name which can be used for a majority of cases. Then when a non conforming case is encountered, we can make a new TO element for it.
Here's a description of what seems to be the most common transistor outline configurations:
The process of using a transistor for the first time in a gschem to PCB design takes these steps (2N3904 used as an example):
tutorial by Bill Wilson (bill–at–gkrellm.net)