DPDK 22.11.5
rte_eth_ctrl.h
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1/* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation
3 */
4
5#ifndef _RTE_ETH_CTRL_H_
6#define _RTE_ETH_CTRL_H_
7
8#include <stdint.h>
9#include <rte_common.h>
10#include <rte_ether.h>
11#include "rte_flow.h"
12#include "rte_ethdev.h"
13
22#ifdef __cplusplus
23extern "C" {
24#endif
25
30#define RTE_NTUPLE_FLAGS_DST_IP 0x0001
31#define RTE_NTUPLE_FLAGS_SRC_IP 0x0002
32#define RTE_NTUPLE_FLAGS_DST_PORT 0x0004
33#define RTE_NTUPLE_FLAGS_SRC_PORT 0x0008
34#define RTE_NTUPLE_FLAGS_PROTO 0x0010
35#define RTE_NTUPLE_FLAGS_TCP_FLAG 0x0020
37#define RTE_5TUPLE_FLAGS ( \
38 RTE_NTUPLE_FLAGS_DST_IP | \
39 RTE_NTUPLE_FLAGS_SRC_IP | \
40 RTE_NTUPLE_FLAGS_DST_PORT | \
41 RTE_NTUPLE_FLAGS_SRC_PORT | \
42 RTE_NTUPLE_FLAGS_PROTO)
43
44#define RTE_2TUPLE_FLAGS ( \
45 RTE_NTUPLE_FLAGS_DST_PORT | \
46 RTE_NTUPLE_FLAGS_PROTO)
47
48#define RTE_NTUPLE_TCP_FLAGS_MASK 0x3F
55 uint16_t flags;
56 uint32_t dst_ip;
57 uint32_t dst_ip_mask;
58 uint32_t src_ip;
59 uint32_t src_ip_mask;
60 uint16_t dst_port;
61 uint16_t dst_port_mask;
62 uint16_t src_port;
63 uint16_t src_port_mask;
64 uint8_t proto;
65 uint8_t proto_mask;
69 uint8_t tcp_flags;
70 uint16_t priority;
72 uint16_t queue;
73};
74
75#define RTE_ETH_FDIR_MAX_FLEXLEN 16
76#define RTE_ETH_INSET_SIZE_MAX 128
82 RTE_ETH_INPUT_SET_UNKNOWN = 0,
83
84 /* L2 */
85 RTE_ETH_INPUT_SET_L2_SRC_MAC = 1,
86 RTE_ETH_INPUT_SET_L2_DST_MAC,
87 RTE_ETH_INPUT_SET_L2_OUTER_VLAN,
88 RTE_ETH_INPUT_SET_L2_INNER_VLAN,
89 RTE_ETH_INPUT_SET_L2_ETHERTYPE,
90
91 /* L3 */
92 RTE_ETH_INPUT_SET_L3_SRC_IP4 = 129,
93 RTE_ETH_INPUT_SET_L3_DST_IP4,
94 RTE_ETH_INPUT_SET_L3_SRC_IP6,
95 RTE_ETH_INPUT_SET_L3_DST_IP6,
96 RTE_ETH_INPUT_SET_L3_IP4_TOS,
97 RTE_ETH_INPUT_SET_L3_IP4_PROTO,
98 RTE_ETH_INPUT_SET_L3_IP6_TC,
99 RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
100 RTE_ETH_INPUT_SET_L3_IP4_TTL,
101 RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
102
103 /* L4 */
104 RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT = 257,
105 RTE_ETH_INPUT_SET_L4_UDP_DST_PORT,
106 RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT,
107 RTE_ETH_INPUT_SET_L4_TCP_DST_PORT,
108 RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT,
109 RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT,
110 RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
111
112 /* Tunnel */
113 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC = 385,
114 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_SRC_MAC,
115 RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
116 RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
117 RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY,
118
119 /* Flexible Payload */
120 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD = 641,
121 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
122 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
123 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
124 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
125 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
126 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
127 RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
128
129 RTE_ETH_INPUT_SET_DEFAULT = 65533,
130 RTE_ETH_INPUT_SET_NONE = 65534,
131 RTE_ETH_INPUT_SET_MAX = 65535,
132};
133
138 RTE_ETH_INPUT_SET_OP_UNKNOWN,
141 RTE_ETH_INPUT_SET_OP_MAX
142};
143
144
150 uint16_t flow_type;
151 uint16_t inset_size;
154};
155
160 uint16_t ether_type;
161};
162
167 uint32_t src_ip;
168 uint32_t dst_ip;
169 uint8_t tos;
170 uint8_t ttl;
171 uint8_t proto;
172};
173
179 uint16_t src_port;
180 uint16_t dst_port;
181};
182
188 uint16_t src_port;
189 uint16_t dst_port;
190};
191
197 uint16_t src_port;
198 uint16_t dst_port;
199 uint32_t verify_tag;
200};
201
206 uint32_t src_ip[4];
207 uint32_t dst_ip[4];
208 uint8_t tc;
209 uint8_t proto;
210 uint8_t hop_limits;
211};
212
218 uint16_t src_port;
219 uint16_t dst_port;
220};
221
227 uint16_t src_port;
228 uint16_t dst_port;
229};
230
236 uint16_t src_port;
237 uint16_t dst_port;
238 uint32_t verify_tag;
239};
240
246};
247
252 RTE_FDIR_TUNNEL_TYPE_UNKNOWN = 0,
253 RTE_FDIR_TUNNEL_TYPE_NVGRE,
254 RTE_FDIR_TUNNEL_TYPE_VXLAN,
255};
256
264 uint32_t tunnel_id;
266};
267
273 struct rte_eth_l2_flow l2_flow;
274 struct rte_eth_udpv4_flow udp4_flow;
275 struct rte_eth_tcpv4_flow tcp4_flow;
276 struct rte_eth_sctpv4_flow sctp4_flow;
277 struct rte_eth_ipv4_flow ip4_flow;
278 struct rte_eth_udpv6_flow udp6_flow;
279 struct rte_eth_tcpv6_flow tcp6_flow;
280 struct rte_eth_sctpv6_flow sctp6_flow;
281 struct rte_eth_ipv6_flow ipv6_flow;
282 struct rte_eth_mac_vlan_flow mac_vlan_flow;
283 struct rte_eth_tunnel_flow tunnel_flow;
284};
285
290 uint16_t vlan_tci;
293 uint8_t is_vf;
294 uint16_t dst_id;
295};
296
301 uint16_t flow_type;
306};
307
312 RTE_ETH_FDIR_ACCEPT = 0,
313 RTE_ETH_FDIR_REJECT,
314 RTE_ETH_FDIR_PASSTHRU,
315};
316
326};
327
332 uint16_t rx_queue;
335 uint8_t flex_off;
339};
340
345 uint32_t soft_id;
349};
350
356 uint16_t vlan_tci_mask;
372};
373
378 RTE_ETH_PAYLOAD_UNKNOWN = 0,
379 RTE_ETH_RAW_PAYLOAD,
380 RTE_ETH_L2_PAYLOAD,
381 RTE_ETH_L3_PAYLOAD,
382 RTE_ETH_L4_PAYLOAD,
383 RTE_ETH_PAYLOAD_MAX = 8,
384};
385
397};
398
404 uint16_t flow_type;
407};
408
414 uint16_t nb_payloads;
415 uint16_t nb_flexmasks;
416 struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX];
418 struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX];
420};
421
431};
432
433#define UINT64_BIT (CHAR_BIT * sizeof(uint64_t))
434#define RTE_FLOW_MASK_ARRAY_SIZE \
435 (RTE_ALIGN(RTE_ETH_FLOW_MAX, UINT64_BIT)/UINT64_BIT)
436
446 struct rte_eth_fdir_masks mask;
449 uint32_t guarant_spc;
450 uint32_t best_spc;
452 uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE];
469};
470
476 uint32_t collision;
477 uint32_t free;
478 uint32_t maxhash;
481 uint32_t maxlen;
482 uint64_t add;
483 uint64_t remove;
484 uint64_t f_add;
485 uint64_t f_remove;
486 uint32_t guarant_cnt;
487 uint32_t best_cnt;
488};
489
490#ifdef __cplusplus
491}
492#endif
493
494#endif /* _RTE_ETH_CTRL_H_ */
#define RTE_ETH_INSET_SIZE_MAX
Definition: rte_eth_ctrl.h:76
rte_eth_fdir_behavior
Definition: rte_eth_ctrl.h:311
rte_eth_fdir_tunnel_type
Definition: rte_eth_ctrl.h:251
rte_eth_input_set_field
Definition: rte_eth_ctrl.h:81
rte_eth_fdir_status
Definition: rte_eth_ctrl.h:321
@ RTE_ETH_FDIR_NO_REPORT_STATUS
Definition: rte_eth_ctrl.h:322
@ RTE_ETH_FDIR_REPORT_ID_FLEX_4
Definition: rte_eth_ctrl.h:324
@ RTE_ETH_FDIR_REPORT_FLEX_8
Definition: rte_eth_ctrl.h:325
@ RTE_ETH_FDIR_REPORT_ID
Definition: rte_eth_ctrl.h:323
rte_fdir_mode
Definition: rte_eth_ctrl.h:425
@ RTE_FDIR_MODE_NONE
Definition: rte_eth_ctrl.h:426
@ RTE_FDIR_MODE_PERFECT
Definition: rte_eth_ctrl.h:428
@ RTE_FDIR_MODE_SIGNATURE
Definition: rte_eth_ctrl.h:427
@ RTE_FDIR_MODE_PERFECT_TUNNEL
Definition: rte_eth_ctrl.h:430
@ RTE_FDIR_MODE_PERFECT_MAC_VLAN
Definition: rte_eth_ctrl.h:429
rte_filter_input_set_op
Definition: rte_eth_ctrl.h:137
@ RTE_ETH_INPUT_SET_SELECT
Definition: rte_eth_ctrl.h:139
@ RTE_ETH_INPUT_SET_ADD
Definition: rte_eth_ctrl.h:140
rte_eth_payload_type
Definition: rte_eth_ctrl.h:377
#define RTE_ETH_FDIR_MAX_FLEXLEN
Definition: rte_eth_ctrl.h:75
enum rte_eth_fdir_status report_status
Definition: rte_eth_ctrl.h:334
enum rte_eth_fdir_behavior behavior
Definition: rte_eth_ctrl.h:333
struct rte_eth_fdir_input input
Definition: rte_eth_ctrl.h:347
struct rte_eth_fdir_action action
Definition: rte_eth_ctrl.h:348
struct rte_eth_flex_payload_cfg flex_set[RTE_ETH_PAYLOAD_MAX]
Definition: rte_eth_ctrl.h:416
struct rte_eth_fdir_flex_mask flex_mask[RTE_ETH_FLOW_MAX]
Definition: rte_eth_ctrl.h:418
uint8_t mask[RTE_ETH_FDIR_MAX_FLEXLEN]
Definition: rte_eth_ctrl.h:405
uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN]
Definition: rte_eth_ctrl.h:291
uint32_t guarant_spc
Definition: rte_eth_ctrl.h:449
uint32_t flex_payload_unit
Definition: rte_eth_ctrl.h:456
uint64_t flow_types_mask[RTE_FLOW_MASK_ARRAY_SIZE]
Definition: rte_eth_ctrl.h:452
uint32_t max_flex_bitmask_num
Definition: rte_eth_ctrl.h:468
uint32_t flex_bitmask_unit
Definition: rte_eth_ctrl.h:466
uint32_t max_flexpayload
Definition: rte_eth_ctrl.h:453
struct rte_eth_fdir_flex_conf flex_conf
Definition: rte_eth_ctrl.h:448
uint16_t flex_payload_limit
Definition: rte_eth_ctrl.h:463
enum rte_fdir_mode mode
Definition: rte_eth_ctrl.h:445
uint32_t max_flex_payload_segment_num
Definition: rte_eth_ctrl.h:459
struct rte_eth_fdir_flow_ext flow_ext
Definition: rte_eth_ctrl.h:304
union rte_eth_fdir_flow flow
Definition: rte_eth_ctrl.h:302
uint16_t vlan_tci_mask
Definition: rte_eth_ctrl.h:356
uint8_t mac_addr_byte_mask
Definition: rte_eth_ctrl.h:367
uint16_t src_port_mask
Definition: rte_eth_ctrl.h:362
uint32_t tunnel_id_mask
Definition: rte_eth_ctrl.h:369
uint8_t tunnel_type_mask
Definition: rte_eth_ctrl.h:370
struct rte_eth_ipv6_flow ipv6_mask
Definition: rte_eth_ctrl.h:360
struct rte_eth_ipv4_flow ipv4_mask
Definition: rte_eth_ctrl.h:358
uint16_t dst_port_mask
Definition: rte_eth_ctrl.h:364
enum rte_eth_payload_type type
Definition: rte_eth_ctrl.h:391
uint16_t src_offset[RTE_ETH_FDIR_MAX_FLEXLEN]
Definition: rte_eth_ctrl.h:392
uint32_t dst_ip[4]
Definition: rte_eth_ctrl.h:207
uint32_t src_ip[4]
Definition: rte_eth_ctrl.h:206
uint16_t ether_type
Definition: rte_eth_ctrl.h:160
struct rte_ether_addr mac_addr
Definition: rte_eth_ctrl.h:245
struct rte_eth_ipv4_flow ip
Definition: rte_eth_ctrl.h:196
struct rte_eth_ipv6_flow ip
Definition: rte_eth_ctrl.h:235
struct rte_eth_ipv4_flow ip
Definition: rte_eth_ctrl.h:187
struct rte_eth_ipv6_flow ip
Definition: rte_eth_ctrl.h:226
struct rte_ether_addr mac_addr
Definition: rte_eth_ctrl.h:265
enum rte_eth_fdir_tunnel_type tunnel_type
Definition: rte_eth_ctrl.h:262
struct rte_eth_ipv4_flow ip
Definition: rte_eth_ctrl.h:178
struct rte_eth_ipv6_flow ip
Definition: rte_eth_ctrl.h:217