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IndustrialPCI

PCI=Peripheral Component Interconnect.
IndustrialPCI is a version of PCI adapted for industrial and/or embedded applications.

The IPCI connector has three parts:

UNKNOWN (at the backplane)
UNKNOWN (at the device (card))

UNKNOWN CONNECTOR at the backplane.
UNKNOWN CONNECTOR at the device (card).

System Slot (Middle)

Pin Name Description Note
A1 +3,3V +3.3 VDC  
A2 AD2 Address 2  
A3 AD6 Address 6  
A4 GND Ground  
A5 AD10 Address 10  
A6 AD13 Address 13  
A7 GND Ground  
A8 SDONE Snoop Done 1
A9 GND Ground  
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18  
A12 GND Ground  
A13 +5V +5 VDC  
A14 AD24 Address 24  
A15 AD27 Address 27  
A16 GND Ground  
A17 REQ2 Request 2 1
A18 GND Ground  
A19 CLK1 33 or 66 MHz Clock  
A20 CLK2    
A21 GND Ground  
A22 CLK3    
A23 CLK4    
A24 +3,3V +3.3 VDC  
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3  
B3 +5V +5 VDC  
B4 AD8 Address 8  
B5 +3,3V +3.3 VDC  
B6 AD14 Address 14  
B7 PAR Parity  
B8 +3,3V +3.3 VDC  
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2  
B11 V(I/O) +3.3 or +5 VDC  
B12 AD21 Address 21  
B13 +3,3V +3.3 VDC  
B14 V(I/O) +3.3 or +5 VDC  
B15 AD28 Address 28  
B16 AD31 Address 31  
B17 +3,3V +3.3 VDC  
B18 GNT3 Grant 3  
B19 RST# Reset  
B20 NMI# Non Maskable Interrupt  
B21 X6 Reserved (6)  
B22 +5V +5 VDC :
B23 RSTIN#   2
B24 USB+ Universal Serial Bus (USB)(+)  
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground  
C3 AD7 Address 7  
C4 AD9 Address 9  
C5 AD11 Address 11  
C6 GND Ground  
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground  
C11 AD19 Address 19  
C12 AD22 Address 22  
C13 GND Ground  
C14 AD25 Address 25  
C15 GND Ground  
C16 X1 Reserved (1)  
C17 GNT2 Grant 2  
C18 REQ4 Request 4 1
C19 SLEEP#/SDAT Sleep/Serial Data (I2C) 3
C20 X4 Reserved (4)  
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC  
C24 USB- Universal Serial Bus (USB)(-)  
D1 AD0 Address 0  
D2 AD4 Address 4  
D3 C/BE0# Command, Byte Enable 0  
D4 +3,3V +3.3 VDC  
D5 AD12 Address 12  
D6 AD15 Address 15  
D7 V(I/O) +3.3 or +5 VDC  
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16  
D11 AD20 Address 20  
D12 +5V +5 VDC  
D13 +5V +5 VDC  
D14 AD26 Address 26  
D15 AD29 Address 29  
D16 REQ1 Request 1 1
D17 REQ3 Request 3 1
D18 V(I/O) +3.3 or +5 VDC  
D19 X2 Reserved (2)  
D20 X5 Reserved (5)  
D21 +3,3V +3.3 VDC  
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)    
E1 AD1 Address 1  
E2 AD5 Address 5  
E3 GND Ground  
E4 M66EN Enable 66Mhz PCI-bus  
E5 GND Ground  
E6 C/BE1# Command, Byte Enable 1  
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC  
E9 IRDY# Initiator Ready 1
E10 AD17 Address 17  
E11 GND Ground  
E12 AD23 Address 23  
E13 C/BE3# Command, Byte Enable 3  
E14 GND Ground  
E15 AD30 Address 30  
E16 GNT1 Grant 1  
E17 +5V +5 VDC  
E18 GNT4 Grant 4  
E19 X3 Reserved (3)  
E20 GND Ground  
E21 INTC# Interrupt C 1
E22 -12V -12 VDC  
E23 +12V +12 VDC  
E24 VBATT    

1 = Pullup resistor of 2,7 kOhm on the System Slot (CPU).
2 = Pullup resistor of 330 ohm on the System Slot (CPU).
3 = Pullup resistor of 4,7 KB ohm, if not supported by the System Slot (CPU).

Module Bus Slot (Middle)

Pin Name Description Note
A1 +3,3V +3.3 VDC  
A2 AD2 Address 2  
A3 AD6 Address 6  
A4 GND Ground  
A5 AD10 Address 10  
A6 AD13 Address 13  
A7 GND Ground  
A8 SDONE Snoop Done 1
A9 GND Ground  
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18  
A12 GND Ground  
A13 +5V +5 VDC  
A14 AD24 Address 24  
A15 AD27 Address 27  
A16 GND Ground  
A17 REQ2 Request 2 1
A18 CLKM    
A19 CLK1 33 or 66 MHz Clock  
A20 CLK2    
A21 GND Ground  
A22 CLK3    
A23 CLK4    
A24 +3,3V +3.3 VDC  
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3  
B3 +5V +5 VDC  
B4 AD8 Address 8  
B5 +3,3V +3.3 VDC  
B6 AD14 Address 14  
B7 PAR Parity  
B8 +3,3V +3.3 VDC  
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2  
B11 V(I/O) +3.3 or +5 VDC  
B12 AD21 Address 21  
B13 +3,3V +3.3 VDC  
B14 V(I/O) +3.3 or +5 VDC  
B15 AD28 Address 28  
B16 AD31 Address 31  
B17 +3,3V +3.3 VDC  
B18 GNT3 Grant 3  
B19 RST# Reset  
B20 NMI# Non Maskable Interrupt  
B21 X6 Reserved (6)  
B22 +5V +5 VDC :
B23 RSTIN#    
B24 USB+ Universal Serial Bus (USB)(+)  
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground  
C3 AD7 Address 7  
C4 AD9 Address 9  
C5 AD11 Address 11  
C6 GND Ground  
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground  
C11 AD19 Address 19  
C12 AD22 Address 22  
C13 GND Ground  
C14 AD25 Address 25  
C15 GND Ground  
C16 X1 Reserved (1)  
C17 GNT2 Grant 2  
C18 REQ4 Request 4 1
C19 SLEEP#/SDAT Sleep/Serial Data (I2C)  
C20 X4 Reserved (4)  
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC  
C24 USB- Universal Serial Bus (USB)(-)  
D1 AD0 Address 0  
D2 AD4 Address 4  
D3 C/BE0# Command, Byte Enable 0  
D4 +3,3V +3.3 VDC  
D5 AD12 Address 12  
D6 AD15 Address 15  
D7 V(I/O) +3.3 or +5 VDC  
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16  
D11 AD20 Address 20  
D12 +5V +5 VDC  
D13 +5V +5 VDC  
D14 AD26 Address 26  
D15 AD29 Address 29  
D16 REQ1 Request 1 1
D17 REQ3 Request 3 1
D18 V(I/O) +3.3 or +5 VDC  
D19 X2 Reserved (2)  
D20 X5 Reserved (5)  
D21 +3,3V +3.3 VDC  
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)    
E1 AD1 Address 1  
E2 AD5 Address 5  
E3 GND Ground  
E4 M66EN Enable 66Mhz PCI-bus  
E5 GND Ground  
E6 C/BE1# Command, Byte Enable 1  
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC  
E9 IRDY# Initiator Ready 1
E10 AD17 Address 17  
E11 GND Ground  
E12 AD23 Address 23  
E13 C/BE3# Command, Byte Enable 3  
E14 GND Ground  
E15 AD30 Address 30  
E16 GNT1 Grant 1  
E17 +5V +5 VDC  
E18 GNT4 Grant 4  
E19 X3 Reserved (3)  
E20 GND Ground  
E21 INTC# Interrupt C 1
E22 -12V -12 VDC  
E23 +12V +12 VDC  
E24 VBATT    

1 = Pullup resistor of 2,7 kOhm on the System Slot (CPU).

Card Slot (Middle)

Pin Name Description Note
A1 +3,3V +3.3 VDC  
A2 AD2 Address 2  
A3 AD6 Address 6  
A4 GND Ground  
A5 AD10 Address 10  
A6 AD13 Address 13  
A7 GND Ground  
A8 SDONE Snoop Done 1
A9 GND Ground  
A10 FRAME# Indicate Address or Data phase 1
A11 AD18 Address 18  
A12 GND Ground  
A13 +5V +5 VDC  
A14 AD24 Address 24  
A15 AD27 Address 27  
A16 GND Ground  
A17 IDSEL0 IDSEL0 1
A18 GND Ground  
A19 CLK1 33 or 66 MHz Clock  
A20 GND Ground  
A21 GND Ground  
A22 GND Ground  
A23 GND Ground  
A24 +3,3V +3.3 VDC  
B1 REQ64# Request 64 ??? 1
B2 AD3 Address 3  
B3 +5V +5 VDC  
B4 AD8 Address 8  
B5 +3,3V +3.3 VDC  
B6 AD14 Address 14  
B7 PAR Parity  
B8 +3,3V +3.3 VDC  
B9 STOP# Stop 1
B10 C/BE2# Command, Byte Enable 2  
B11 V(I/O) +3.3 or +5 VDC  
B12 AD21 Address 21  
B13 +3,3V +3.3 VDC  
B14 V(I/O) +3.3 or +5 VDC  
B15 AD28 Address 28  
B16 AD31 Address 31  
B17 +3,3V +3.3 VDC  
B18 GND Ground  
B19 RST# Reset  
B20 NMI# Non Maskable Interrupt  
B21 X6 Reserved (6)  
B22 +5V +5 VDC :
B23 RSTIN#    
B24 USB+ Universal Serial Bus (USB)(+)  
C1 ACK64# Acknowledge 64 ??? 1
C2 GND Ground  
C3 AD7 Address 7  
C4 AD9 Address 9  
C5 AD11 Address 11  
C6 GND Ground  
C7 SERR# System Error 1
C8 PERR# Parity Error 1
C9 DEVSEL# Device Select 1
C10 GND Ground  
C11 AD19 Address 19  
C12 AD22 Address 22  
C13 GND Ground  
C14 AD25 Address 25  
C15 GND Ground  
C16 X1 Reserved (1)  
C17 IDSEL1 Initialization Device Select 1  
C18 GND Ground  
C19 SLEEP#/SDAT Sleep/Serial Data (I2C)  
C20 X4 Reserved (4)  
C21 INTD# Interrupt D 1
C22 INTB# Interrupt B 1
C23 +5V +5 VDC  
C24 USB- Universal Serial Bus (USB)(-)  
D1 AD0 Address 0  
D2 AD4 Address 4  
D3 C/BE0# Command, Byte Enable 0  
D4 +3,3V +3.3 VDC  
D5 AD12 Address 12  
D6 AD15 Address 15  
D7 V(I/O) +3.3 or +5 VDC  
D8 LOCK# Resource Lock 1
D9 TRDY# Test Logic Ready 1
D10 AD16 Address 16  
D11 AD20 Address 20  
D12 +5V +5 VDC  
D13 +5V +5 VDC  
D14 AD26 Address 26  
D15 AD29 Address 29  
D16 REQ1 Request 1 1
D17 IDSEL2 Initialization Device Select 2  
D18 V(I/O) +3.3 or +5 VDC  
D19 X2 Reserved (2)  
D20 X5 Reserved (5)  
D21 +3,3V +3.3 VDC  
D22 INTA# Interrupt A 1
D23 ICPEN#/SCLK ICPEN/Serial Clock (I2C) 3
D24 OSC (PWDN)    
E1 AD1 Address 1  
E2 AD5 Address 5  
E3 GND Ground  
E4 M66EN Enable 66Mhz PCI-bus  
E5 GND Ground  
E6 C/BE1# Command, Byte Enable 1  
E7 SBO# Snoop Backoff 1
E8 +5V +5 VDC  
E9 IRDY# Initiator Ready 1
E10 AD17 Address 17  
E11 GND Ground  
E12 AD23 Address 23  
E13 C/BE3# Command, Byte Enable 3  
E14 GND Ground  
E15 AD30 Address 30  
E16 GNT1 Grant 1  
E17 +5V +5 VDC  
E18 GNT4 Grant 4  
E19 X3 Reserved (3)  
E20 GND Ground  
E21 INTC# Interrupt C 1
E22 -12V -12 VDC  
E23 +12V +12 VDC  
E24 VBATT    

1 = Pullup resistor of 2,7 kOhm on the System Slot (CPU).

64-bit PCI (Top)

Pin Name Description Note
A1 GND Ground  
A2 X10 Reserved (10)  
A3 AD35 Address 35 2
A4 AD38 Address 38 2
A5 AD42 Address 42 2
A6 V(I/O) +3.3 or +5 VDC  
A7 V(I/O) +3.3 or +5 VDC  
A8 AD52 Address 52 2
A9 AD56 Address 56 2
A10 AD60 Address 60 2
A11 AD63 Address 63 2
A12 GND Ground  
B1 X7 Reserved (7)  
B2 GND Ground  
B3 AD36 Address 36 2
B4 AD39 Address 39 2
B5 AD43 Address 43 2
B6 AD46 Address 46 2
B7 AD49 Address 49 2
B8 AD53 Address 53 2
B9 AD57 Address 57 2
B10 AD61 Address 61 2
B11 GND Ground  
B12 C/BE6# Command, Byte Enable 6 2
C1 X8 Reserved (8)  
C2 AD32 Address 32 2
C3 GND Ground  
C4 AD40 Address 40 2
C5 AD44 Address 44 2
C6 GND Ground  
C7 GND Ground  
C8 AD54 Address 54 2
C9 AD58 Address 58 2
C10 GND Ground  
C11 PAR64 Parity 64 ??? 2
C12 C/BE7# Command, Byte Enable 7 2
D1 X9 Reserved (9)  
D2 AD33 Address 33 2
D3 AD37 Address 37 2
D4 GND Ground  
D5 AD45 Address 45 2
D6 AD47 Address 47 2
D7 AD50 Address 50 2
D8 AD55 Address 55 2
D9 GND Ground  
D10 AD62 Address 62 2
D11 C/BE4# Command, Byte Enable 4 2
D12 X11 Reserved (11)  
E1 GND Ground  
E2 AD34 Address 34 2
E3 V(I/O) +3.3 or +5 VDC  
E4 AD41 Address 41 2
E5 GND Ground  
E6 AD48 Address 48 2
E7 AD51 Address 51 2
E8 GND Ground  
E9 AD59 Address 59 2
E10 V(I/O) +3.3 or +5 VDC  
E11 C/BE5# Command, Byte Enable 5 2
E12 X12 Reserved (12)  

2 = Pullup resistor of 2,7 kOhm (5V bus system) or 8,2 kOhm (3,3V bus system) on the backplane.

ISA96/AT96 (Bottom)

Pin Name Description Note
A1 RSTDRV    
A2 IRQ9 Interrupt 9  
A3 SD11 Data 11  
A4 SD9 Data 9  
A5 IOCHRDY   1
A6 IOW# I/O Write  
A7 SA15 Address 15  
A8 CLK Clock  
A9 SA10 Address 10  
A10 SA7 Address 7  
A11 T/C    
A12 SA2 Address 2  
B1 SD15 Data 15  
B2 SD13 Data 13  
B3 SD3 Data 3  
B4 SD1 Data 1  
B5 SMEMW# System Memory Write  
B6 SA18 Address 18  
B7 SA14 Address 14  
B8 DACK6# DMA Acknowledge 6  
B9 SA9 Address 9  
B10 IRQ3 Interrupt 3  
B11 IOCS16# I/O 16-bit chip select 1
B12 SA1 Address 1  
C1 SD7 Data 7  
C2 SD5 Data 5  
C3 SD10 Data 10  
C4 SD8 Data 8  
C5 AEN Address Enable  
C6 IOR# I/O Read  
C7 SA13 Address 13  
C8 SA11 Address 11  
C9 IRQ5 Interrupt 5  
C10 SA6 Address 6  
C11 SA4 Address 4  
C12 IRQ11 Interrupt 11  
D1 SD14 Data 14  
D2 SD12 Data 12  
D3 SD2 Data 2  
D4 SD0 Data 0  
D5 SMEMR# System Memory Read  
D6 SA17 Address 17  
D7 REF#    
D8 IRQ7 Interrupt 7  
D9 SA8 Address 8  
D10 MCS16#   1
D11 BALE    
D12 SA0 Address 0  
E1 SD6 Data 6  
E2 SD4 Data 4  
E3 0WS   1
E4 SBHE#    
E5 SA19 Address 19  
E6 SA16 Address 16  
E7 SA12 Address 12  
E8 DRQ6 DMA Request 6  
E9 IRQ4 Interrupt 4  
E10 SA5 Address 5  
E11 SA3 Address 3  
E12 IRQ10 Interrupt 10  

1 = Pullup resistor must be integrated into the System Slot (CPU).

VMEbus (Bottom)

Pin Name Description
A1 D0 Data 0
A2 D2 Data 2
A3 D12 Data 12
A4 D7 Data 7
A5 DS1#  
A6 BR3#  
A7 AM1  
A8 AM3  
A9 IACKOUT#  
A10 A14 Address 14
A11 A12 Address 12
A12 A10 Address 10
B1 BBSY#  
B2 D10 Data 10
B3 D5 Data 5
B4 D15 Data 15
B5 SYSRES#  
B6 A23 Address 23
B7 A21 Address 21
B8 A19 Address 19
B9 A16 Address 16
B10 A6 Address 6
B11 A4 Address 4
B12 A2 Address 2
C1 D8 Data 8
C2 D3 Data 3
C3 D13 Data 13
C4 SYSCLK  
C5 DS0#  
C6 DTACK#  
C7 AS#  
C8 IACK#  
C9 AM4  
C10 A13 Address 13
C11 A11 Address 11
C12 A9 Address 9
D1 D1 Data 1
D2 D11 Data 11
D3 D6 Data 6
D4 BG3OUT#  
D5 WR# Write
D6 AM0  
D7 AM2  
D8 A18 Address 18
D9 A15 Address 15
D10 A5 Address 5
D11 A3 Address 3
D12 A1 Address 1
E1 D9 Data 9
E2 D4 Data 4
E3 D14 Data 14
E4 BERR# Bus Error
E5 AM5  
E6 A22 Address 22
E7 A20 Address 20
E8 A17 Address 17
E9 A7 Address 7
E10 IRQ5# Interrupt 5
E11 IRQ3# Interrupt 3
E12 A8 Address 8

ECB (Bottom)

Pin Name Description
A1 D5 Data 5
A2 D2 Data 2
A3 A4 Data 4
A4 A7 Address 7
A5 BAI  
A6 2F  
A7 A10 Address 10
A8 INT#  
A9 VCMOS  
A10 PWRCLR#  
A11 A13 Address 13
A12 RESET# Reset
B1 D0 Data 0
B2 D4 Data 4
B3 A1 Address 1
B4 WAIT#  
B5 A17 Address 17
B6 IEO  
B7 n/c Not connected
B8 DMARDY  
B9 RD# Read
B10 IORQ#  
B11 ?  
B12 n/c Not connected
C1 D6 Data 6
C2 A0 Address 0
C3 A5 Address 5
C4 A16 Address 16
C5 A18 Address 18
C6 BAO  
C7 M1#  
C8 WR#  
C9 n  
C10 A12 Address 12
C11 A9 Address 9
C12 n/c Not connected
D1 D7 Data 7
D2 A2 Address 2
D3 A8 Address 8
D4 BUSRQ#  
D5 A19 Address 19
D6 A11 Address 11
D7 NMI# Non Maskable Interrupt
D8 PF  
D9 HALT#  
D10 RFSH#  
D11 MRQ#  
D12 n/c Not connected
E1 D3 Data 3
E2 A3 Address 3
E3 A6 Address 6
E4 IEI  
E5 D1 Data 1
E6 A14 Address 14
E7 n/c Not connected
E8 n/c Not connected
E9 DESLCT#  
E10 A15 Address 15
E11 BUSAK#  
E12 n/c Not connected

SMP16 (Bottom)

Pin Name Description
A1 NMI# Non Maskable Interrupt
A2 IRQ0# Interrupt 0
A3 D11 Data 11
A4 D9 Data 9
A5 RDYIN  
A6 IOW#  
A7 A15 Address 15
A8 CLK  
A9 A10 Address 10
A10 A7 Address 7
A11 TC/EOP#  
A12 A2 Address 2
B1 D15 Data 15
B2 D13 Data 13
B3 D3 Data 3
B4 D1 Data 1
B5 MEMW#  
B6 A18 Address 18
B7 A14 Address 14
B8 DACKx#  
B9 A9 Address 9
B10 IRQ3# Interrupt 3
B11 IOCS16#  
B12 A1 Address 1
C1 D7 Data 7
C2 D5 Data 5
C3 D10 Data 10
C4 D8 Data 8
C5 BUSEN  
C6 IOR#  
C7 A13 Address 13
C8 A11 Address 11
C9 IRQ1# Interrupt 1
C10 A6 Address 6
C11 A4 Address 4
C12 IRQ4# Interrupt 4
D1 D14 Data 14
D2 D12 Data 12
D3 D2 Data 2
D4 D0 Data 0
D5 MEMR#  
D6 A17 Address 17
D7 INTA#  
D8 INT#  
D9 A8 Address 8
D10 MECS16#  
D11 ALE  
D12 A0 Address 0
E1 D6 Data 6
E2 D4 Data 4
E3 MMIO#  
E4 BHEN  
E5 A19 Address 19
E6 A16 Address 16
E7 A12 Address 12
E8 DRQx#  
E9 IRQ2# Interrupt 2
E10 A5 Address 5
E11 A3 Address 3
E12 IRQ5# Interrupt 5

Floppy/EIDE (Bottom)

Pin Name Description
A1 FDSEL1 Floppy Select 1
A2 FDSEL0 Floppy Select 0
A3 FDME1 Floppy ?
A4 DIR Floppy Direction
A5 STEP Floppy Step
A6 WRDATA Floppy Write Data
A7 WE Floppy Write?
A8 TRK0 Floppy Track 0
A9 WP Floppy Write?
A10 RDDATA Floppy ?
A11 HDSEL Floppy HD Select
A12 DSKCHG Floppy DiskChange
B1 DRVDEN1 ?
B2 DRVDEN0 ?
B3 IDECS3P# IDE ?
B4 IDEA2 IDE ?
B5 IDEIRQS IDE ?
B6 IDEPUS IDE ?
B7 IDEDRQP IDE ?
B8 IDED14 IDE Data 14
B9 IDED8 IDE Data 8
B10 IDED6 IDE Data 6
B11 IDED11 IDE Data 11
B12 IDED3 IDE Data 3
C1 FDME0 Floppy Me?
C2 INDX Floppy Index
C3 IDECS3S# IDE ?
C4 IDEA0 IDE ?
C5 IDEDAKS# IDE ?
C6 IDEIOR# IDE ?
C7 IDEDRQS IDE ?
C8 IDED1 IDE Data 1
C9 #IDERST IDE ?
C10 IDED10 IDE Data 10
C11 IDED4 IDE Data 4
C12 IDED2 IDE Data 2
D1 IDELEDS# IDE LED ?
D2 IDELEDP# IDE LED ?
D3 IDECS1S# IDE ?
D4 IDEIRQP IDE ?
D5 IDEPUP IDE Pull Up ?
D6 IDEIOW# IDE ?
D7 IDED15 IDE Data 15
D8 IDED13 IDE Data 13
D9 IDED7 IDE Data 7
D10 GND Ground
D11 GND Ground
D12 GND Ground
E1 GND Ground
E2 GND Ground
E3 IDECS1P# IDE ?
E4 IDEA1 IDE ?
E5 IDEDAKP# IDE ?
E6 IDEIORDY IDE ?
E7 IDED0 IDE Data 0
E8 IDED12 IDE Data 12
E9 IDED9 IDE Data 9
E10 IDED5 IDE Data 5
E11 GND Ground
E12 GND Ground

SCSI (Bottom)

Pin Name Description
A1 TERM  
A2 GND Ground
A3 I/O#  
A4 REQ#  
A5 ATN#  
A6 D8 Data 8
A7 D9 Data 9
A8 D10 Data 10
A9 D2 Data 2
A10 D4 Data 4
A11 DP0  
A12 GND Ground
B1 TERM  
B2 GND Ground
B3 GND Ground
B4 GND Ground
B5 GND Ground
B6 GND Ground
B7 GND Ground
B8 GND Ground
B9 GND Ground
B10 GND Ground
B11 GND Ground
B12 GND Ground
C1 TERM  
C2 GND Ground
C3 C/D#  
C4 MSG#  
C5 ACK#  
C6 D12 Data 12
C7 DP1 Data P1
C8 D13 Data 13
C9 D1 Data 1
C10 D5 Data 5
C11 D7 Data 7
C12 GND Ground
D1 TERM  
D2 GND Ground
D3 GND Ground
D4 GND Ground
D5 GND Ground
D6 GND Ground
D7 GND Ground
D8 GND Ground
D9 GND Ground
D10 GND Ground
D11 GND Ground
D12 GND Ground
E1 TERM  
E2 GND Ground
E3 SEL#  
E4 RST#  
E5 BSY#  
E6 D14 Data 14
E7 D15 Data 15
E8 D11 Data 11
E9 D0 Data 0
E10 D3 Data 3
E11 D6 Data 6
E12 GND Ground
Contributor: Joakim Ögren, Rob Gill
Source: IndustrialPCI page at Standard Industrial PC Systems's (SIPS) homepage

Copyright © The Hardware Book Team 1996-2004.
May be copied and redistributed, partially or in whole, as appropriate.
Document last modified: 2002-01-10